NOTE
From Copilot
Here’s the straight, engineering‑useful truth: there is no official “PCIe‑approved” 4‑layer stackup, because by Gen4 and above, a 4‑layer board is barely viable and often outright discouraged. But designers still ask for “typical” stackups, so I’ll give you the realistic, industry‑standard patterns and the limits you can expect at each generation.
I’ll break it down cleanly and practically.
🧱 Typical 4‑Layer Stackups by PCIe Generation
Below is what engineers actually use in the field, along with the feasibility notes.
PCIe 3.0 (8 GT/s)
✔️ 4‑layer is viable
Typical stackup:
L1 — Signal (PCIe pairs)
L2 — Solid GND
L3 — Power (split planes) + some low‑speed routing
L4 — Signal (PCIe pairs or misc)
Notes:
- Route PCIe on L1 and/or L4 over continuous L2 ground.
- Keep dielectric thickness ~8–10 mil between L1–L2 to hit ~85 Ω diff.
- Avoid routing PCIe on L3 (reference plane discontinuities).
- Crosstalk is manageable with 4‑layer if spacing is decent.
Verdict: 4‑layer is common and works well.
PCIe 4.0 (16 GT/s)
⚠️ 4‑layer is marginal but possible with tight control
Typical stackup:
L1 — Signal (PCIe)
L2 — Solid GND
L3 — Solid PWR (not split if possible)
L4 — Signal (PCIe or misc)
Key constraints:
- You must maintain a solid reference plane under every PCIe trace.
- Dielectric thickness often needs to be reduced (4–6 mil) to control loss.
- FR‑4 must be low‑loss variant (e.g., Isola 370HR, Panasonic Megtron 4‑class).
- Trace lengths must be short (few inches) to stay within the loss budget.
Verdict: 4‑layer is barely acceptable and only for short, simple links.
PCIe 5.0 (32 GT/s)
❌ 4‑layer is generally NOT recommended
But if someone forces you into it (small carrier boards, SOM breakouts), the “least bad” stackup is:
L1 — Signal (PCIe)
L2 — Solid GND
L3 — Solid PWR (no splits)
L4 — Signal (PCIe)
Why it’s problematic:
- FR‑4 loss is too high at 32 GT/s.
- You need ultra‑low‑loss laminate (Megtron 6, Tachyon 100G, I-Speed).
- You cannot afford any reference plane discontinuities.
- You cannot route PCIe on L3.
- Length budget is extremely short (often <1–2 inches).
Verdict: Only feasible for very short, connector‑adjacent routing on premium materials.
PCIe 6.0 (64 GT/s PAM4)
🚫 4‑layer is effectively impossible
PCIe 6.0 requires:
- Ultra‑low‑loss materials
- Tight insertion‑loss budgets
- Very controlled impedance
- Multi‑plane referencing
- Via backdrilling
- Equalization‑friendly channel design
A 4‑layer board simply cannot meet the loss, crosstalk, or return‑path requirements.
Verdict: 4‑layer is not a realistic option for PCIe 6.0.
📊 Summary Table
| PCIe Gen | Speed | 4‑Layer Feasible? | Typical Stackup | Notes |
|---|---|---|---|---|
| 3.0 | 8 GT/s | ✔️ Yes | L1 SIG / L2 GND / L3 PWR / L4 SIG | Works well with FR‑4 |
| 4.0 | 16 GT/s | ⚠️ Marginal | Same as above | Requires low‑loss FR‑4, short traces |
| 5.0 | 32 GT/s | ❌ Rare | Same as above | Only for ultra‑short links on premium materials |
| 6.0 | 64 GT/s | 🚫 No | N/A | Requires >6 layers |
🧠 A practical rule of thumb
- Gen3: 4 layers is normal
- Gen4: 4 layers is “only if you must”
- Gen5: 6–8 layers is the real minimum
- Gen6: 10–12 layers is typical
If you want, I can also sketch optimal 6‑layer and 8‑layer stackups for Gen4/Gen5/Gen6, including dielectric thicknesses, reference‑plane strategy, and via‑breakout patterns.